Digital Logic Design
Fall 2009
Instructor: Dr. M. Bag-Mohammadi
Email: mozafarb@ece.ut.ac.ir
Assistant: Ghahraman Sayalli
Web log: click here
Office Hours: Click here
Grade:
Text: Digital Design by Mano (4th Edition). The CD-ROM in the back of the book contains a Verilog simulator as well as source code files for all the examples in the book.
Goals
Primary goals of the course are:
|
|
To introduce digital logic design. |
|
|
Specific topics include: Binary systems, Boolean algebra, logic gates, analysis/design of combinatorial circuits, synchronous sequential logic, (If we had enough time we will look at registers, counters, and memory briefly).. |
|
|
To introduce laboratory experiments in digital circuits and logic design; students will construct and test basic digital circuits using standard integrated circuits (ICs). |
|
|
There will be 1 exam during the semester and a final exam at the end of the semester. |
|
|
All exams will be open book and open notes. |
|
|
Assignments are due seven days from the initial day of the assignment (i.e. the following Tuesday). |
|
|
Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. |
|
|
All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. |
|
|
Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams. |
| Topic | Word File |
| Binary systems, Boolean Algebra | hw1-f09.doc |
|
Gate-Level Minimization: Karnaugh Map, Design |
hw2-f09.doc |
| Combinational Logic:Adder, Comparator, Decoder, Multiplexer | hw3-f09.doc |
| Sequential logic: latches, flip-flops, analysis, state diagram | hw4-f09.doc |
| Sequential logic design, register, counter, shift register | hw5-f09.doc |
| PLA, PAL, RAM, PLDs, CPLDS, FPGA, ROM, counter, register | hw6-f09.doc |
Final grades in the course will be based on the following weighting distribution.
|
|
Homework……25% |
|
|
Midterm 1…… 35% |
|
|
Final Exam…..45% |
Students are responsible for their own learning, through reading and studying the text, reviewing the lectures, and working out the homework problems. I strongly advise that you read the upcoming material before it appears in lecture; the material will make much more sense that way.
| Topic | Chapter | Lecture Note |
|
Introduction: Binary Systems |
1 | dlc-1.ppt |
|
Boolean Algebra and Logic Gates |
2 | dlc-2.ppt |
|
Gate-Level Minimization: Karnaugh
|
3 | dlc-3.ppt |
|
Gate-Level Minimization |
3 | dlc-4.ppt |
|
Gate-Level Minimization, Combinational Logic |
3,4 | dlc-5.ppt |
| Combinational Logic | 4 | dlc-6.ppt |
|
Combinational Logic |
4 | dlc-7.ppt |
| Midterm 1 | 1, 2, 3, 4 | dlc-mid-f09.doc |
| Sequential circuit | 5 | dlc-8.ppt |
| Sequential circuit | 5 | dlc-9.ppt |
| Sequential circuit | 5 | dlc-10.ppt |
| register | 6 | dlc-11.ppt |
| counter | 6 | dlc-12.ppt |
| memory | 7 | dlc-13.ppt |
| final | ||
| - |