Instructor: Dr. M. Bag-Mohammadi, Assistants: Majid Fazeli, Mojtaba Fazeli
Grade:Click here
Digital Design by Mano (4th Edition.
The CD-ROM in the back of the book contains a Verilog simulator as well as source code files for all the examples in the book.
Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams.
 1  | Binary systems, Boolean algebra, gate level minimization | assign1-dlc-s16.docx |
 2  | Adder, comparator, multiplexer, decoder, design problems | assign2-dlc-s16.docx |
 3  | Sequential circuit analysis and design, flip-flops, latches | assign3-dlc-s16.docx |
 4  | Sequential circuit design, registers, counters | assign4-dlc-s16.docx |
Final grades in the course will be based on the following weighting distribution.
Topic | Lecture Note |
Introduction: Binary Systems | dlc-1.ppt |
Boolean Algebra and Logic Gates | dlc-2.ppt |
Gate-Level Minimization: Karnaugh | dlc-3.ppt |
Karnaugh map | dlc-4.ppt |
Combinational logic: analysis and design, full adder | dlc-5.ppt |
Full adder, subtract, multiplier, comparator | dlc-6.ppt |
Decoder, multiplexer | dlc-7.ppt |
Midterm | - |
Sequential logic:Latches, Flip flops | dlc-8.ppt |
Sequential logic:Analysis | dlc-9.ppt |
Sequential logic:Design | dlc-10.ppt |
Registers | dlc-11.ppt |
Counters | dlc-12.ppt |
Memory Unit | dlc-13.ppt |
Final | - |