Digital Logic Design
Fall 2008
Instructor: Dr. M. Bag-Mohammadi
Email: mozafarb@ece.ut.ac.ir
Assistant:
Web log: click here
Office Hours: Click here
Grade: dd-f08.xls
Text: Digital Design by Mano (3rd Edition). The CD-ROM in the back of the book contains a Verilog simulator as well as source code files for all the examples in the book.
Goals
Primary goals of the course are:
To introduce digital logic design. | |
Specific topics include: Binary systems, Boolean algebra, logic gates, analysis/design of combinatorial circuits, synchronous sequential logic, (If we had enough time we will look at registers, counters, and memory briefly).. |
To introduce laboratory experiments in digital circuits and logic design; students will construct and test basic digital circuits using standard integrated circuits (ICs). |
There will be 1 exam during the semester and a final exam at the end of the semester. | |
All exams will be open book and open notes. |
Assignments are due seven days from the initial day of the assignment (i.e. the following Tuesday). | |
Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. | |
All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. | |
Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams. |
Topic | Word File | Solution by Ms. Hajar Zeyni-Vand |
Binary systems, Boolean algebra, logic minimization, Karnaugh Map | hw1-f08.doc | Su-h1.doc |
Decoder, comparator, adder, multiplexer | hw2-f08.doc | Su-h2.doc |
Latch, Flip-Flop, analysis and design of sequential circuit | hw3-f08.oc.doc | Su-h3.doc |
hw4-f08.doc | Su-h4.doc |
Final grades in the course will be based on the following weighting distribution.
Homework……20% | |
Midterm 1…… 35% | |
Final Exam…..50% |
Students are responsible for their own learning, through reading and studying the text, reviewing the lectures, and working out the homework problems. I strongly advise that you read the upcoming material before it appears in lecture; the material will make much more sense that way.
Topic | Chapter | Lecture Note |
Introduction: Binary Systems |
1 | dlc-1.ppt |
Boolean Algebra and Logic Gates |
2 | dlc-2.ppt |
Gate-Level Minimization: Karnaugh
|
3 | dlc-3.ppt |
Gate-Level Minimization |
3 | dlc-4.ppt |
Gate-Level Minimization, Combinational Logic |
3, 4 | dlc-5.ppt |
Combinational Logic |
4 | dlc-6.ppt |
Combinational Logic |
4 | dlc-7.ppt |
Midterm 1 | 1, 2, 3, 4 | midterm-f08.doc |
Midterm 2 | 1, 2, 3, 4 | midterm2-f08.doc |
Sequential circuit | 5 | dlc-8.ppt |
Sequential circuit | 5 | dlc-9.ppt |
Sequential circuit | 5 | dlc-10.ppt |
register, | 6 | dlc-11.ppt |
counter | 6 | dlc-12.ppt |
Final | 5, 6 | final-f08.doc |
Lab | - | lab.doc |