Digital Logic Design
Fall 2011
Instructor: Dr. M. Bag-Mohammadi Assistant: Office hours: Click here Grade:
Text: Digital Design by Mano (4th Edition).
The CD-ROM in the back of the book contains a Verilog simulator as well as source code files for all the examples in the book.
Goals
Primary goals of the course are:
|
|
To introduce digital logic design. |
|
|
Specific topics include: Binary systems, Boolean algebra, logic gates, analysis/design of combinatorial circuits, synchronous sequential logic, (If we had enough time we will look at registers, counters, and memory briefly). |
|
|
To introduce laboratory experiments in digital circuits and logic design; students will construct and test basic digital circuits using standard integrated circuits (ICs). |
Exams
|
|
There will be 1 exam during the semester and a final exam at the end of the semester. |
|
|
All exams will be open book and open notes. |
Homework
|
|
Assignments are due seven days from the initial day of the assignment (i.e. the following Tuesday). |
|
|
Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. |
|
|
All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. |
|
|
Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams. |
|
Topic |
Word File |
| Binary systems, Boolean algebra, gate level minimization | assign1-dlc-f11.docx |
| Adder, comparator, multiplexer, decoder, design problems | assign2-dlc-f11.docx |
| Sequential circuit analysis and design, flip-flops, latches | assign3-dlc-f11.docx |
| Sequential circuit design, registers, counters | assign4-dlc-f11.docx |
Grading Policy:
Final grades in the course will be based on the following weighting distribution.
|
|
Homework… 25% |
|
|
Midterm …… 35% |
|
|
Final Exam…..45% |
Lecture Notes:
|
Topic |
Chapter |
Lecture Notes |
|
Introduction: Binary Systems |
1 |
dlc-1.ppt |
|
Boolean Algebra and Logic Gates |
2 |
dlc-2.ppt |
|
Gate-Level Minimization: Karnaugh
|
3 |
dlc-3.ppt |
|
Karnaugh map |
3 |
dlc-4.ppt |
|
Combinational logic: analysis and design, full adder |
4 |
dlc-5.ppt |
|
Full adder, subtract, multiplier, comparator |
4 |
dlc-6.ppt |
|
Decoder, multiplexer |
4 |
dlc-7.ppt |
|
Midterm |
1,2,3,4 |
|
|
Sequential circuits |
5 |
dlc-8.ppt |
|
Sequential circuits |
5 |
dlc-9.ppt |
|
Sequential circuits |
5 |
dlc-10.ppt |
|
Registers |
6 |
dlc-11.ppt |
|
Counters |
6 |
dlc-12.ppt |
|
Memory unit |
7 |
dlc-13.ppt |
|
Final |
dlc-fin-f11.docx |