Computer Architecture
Spring 2015
Computer Architecture is the science and art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. Computer architecture is not about using computers to design buildings.
Goals
Primary goals of the course are:
To introduce computer architecture design. | |
Specific topics include: The design
of computer systems and components. Processor design, instruction
set design, and addressing; control structures and
microprogramming; memory management, caches, and memory
hierarchies; and interrupts and I/O structures |
Logic design and Boolean algebra | |
Assembly language programming | |
Ability to use design tools available on computer |
Introduction, basic computer organization | |
Instruction formats, instruction sets and their design | |
ALU design: Adders, subtracters, logic operations | |
Datapath design | |
Control design: Hardwired control, microprogrammed control | |
More on arithmetic: Multiplication, division, floating point arithmetic | |
RISC machines | |
Pipelining | |
Memory systems and error detection and error correction coding | |
I/O |
There will be 1 exam during the semester and a final exam at the end of the semester. |
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All exams will be open book and open notes. |
Assignments are due seven days from the initial day of the assignment (i.e. the following Sunday). |
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Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. |
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All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. |
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Cooperative group study on the homework is encouraged, but simply copying someone else’s work is unethical and will leave you unprepared for exams. |
Topic | Word File |
Digital logic design | ca-hw1-s15.docx |
Performance evaluation, Ahmdal law, Iron law, Verilog | ca-hw2-s15.doc |
MIPS, arithmetic operation | ca-hw3-s15.doc |
Datapath design, pipeline | ca-hw4-s15.doc |
Cache | - |
Project | Project |
Final grades in the course will be based on the following weighting distribution.
Homework……12% |
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Midterm 1…… 35% |
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Final Exam…..35% |
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Project............18% |
Students are responsible for their own learning, through reading and studying the text, reviewing the lectures, and working out the homework problems. I strongly advise that you read the upcoming material before it appears in lecture; the material will make much more sense that way.
Topic | Chapter | Lecture Note |
Introductionn | 1 | ch1.ppt |
Performance evaluation |
2 | ch2.ppt |
Instruction Set | 3 | ch3.ppt |
Arithmetic 1 | 4 | ch4.ppt |
Verilog | - | Verilog |
Arithmetic 2 | 4 | ch4b.ppt |
Midterm | 1-4 | Midterm |
Simple processor | 5 | ch5.ppt |
Microprogramming | 5 | - |
Pipelining | 6 | ch6.ppt |
Cache design | 7 | ch7.ppt |
Final | 5-7 | final |